1. Field of the Invention
The present invention relates to an arithmetic and logic unit, particularly to a CMOS static arithmetic and logic unit.
2. Description of Related Art
FIG. 1 is a circuit diagram showing a configuration diagram corresponding to one bit of a conventional arithmetic and logic unit (hereinafter to be called ALU).
In the figure, reference numeral 1 designates a first operand input terminal to which a signal A.sub.i (hereinafter to be called a first operand signal) showing a first operand value ("1" or "0") processed in the conventional ALU is inputted, numeral 2 designates a second operand input terminal to which a signal B.sub.i (hereinafter to be called a second operand signal) showing a second operand value ("1" or "0") is inputted, and numeral 3 designates an output terminal (hereinafter to be called an operation result output terminal) which outputs an operation result signal F.sub.i showing a result of an arithmetic and logic operation of the aforesaid two operands.
Numerals 5 to 9 designate signal lines which respectively gives control ! signal S.sub.0, S.sub.1, S.sub.2, S.sub.3 and S.sub.4 for designating an arithmetic/logic operation to be operated by the ALU. Numeral 10 designates an input terminal (hereinafter to be called a carry input terminal) of a carry signal #CY.sub.i-1 (#designates an inverted signal) outputted from a preceding bit, and numeral 11 designates an output terminal (hereinafter to be called a carry output terminal) of a carry signal #CY.sub.i given to a following bit.
Accordingly, when a plurality of the one bit ALUs shown in FIG. 1 are used in parallel, the carry input terminal 10 to which the carry signal #CY.sub.i-1 is inputted of an adjacent one ALU and the carry output terminal 11 which outputs the carry signal #CY.sub.i of the adjacent one bit ALU are connected to each other.
Numeral 12 designates an inverter, and the input thereof is connected to the second operand input terminal.
Numeral 13 designates a first AND gate of three inputs, and the first input thereof is connected to the second operand input terminal 2, the second input to the control signal line 8, and the third input to the first operand input terminal 1.
Numeral 14 designates a second AND gate of three inputs, and the first input thereof is connected to the first operand input terminal 1, the second input to the control signal 7, and the third input to the output of the inverter 12.
Numeral 15 designates a first NOR gate of two inputs, and one input thereof is connected to the output of the first AND gate 13, and the other input to the output of the second AND gate 14.
Numeral 16 designates a third AND gate of two inputs, and the one input, thereof is connected to the output of the inverter 12, and the other input to the control signal line 6.
Numeral 17 designates a fourth AND gate of two inputs, and one input thereof is connected to the control signal line 5, and the other input to the second operand input terminal 2.
Numeral 18 designates a second NOR gate of three inputs, and the first input thereof is connected to the output of the third AND gate 16, the second input to the output of the fourth AND gate 17, and the third input to the first operand input terminal 1.
Numeral 19 designates a first exclusive OR gate (hereinafter to be called EXOR gate) of two inputs, and one input thereof is connected to the output of the first NOR gate 15, and the other input to the output of the second NOR gate 18.
Numeral 20 designates a NAND gate of two inputs, and one input thereof is connected to the control signal line 9, and the other input to the carry input terminal 10.
Numeral 21 designates a second EXOR gate of two inputs, and one input thereof is connected to the output of the first EXOR gate 19, and the other input to the output of the first NAND gate 20.
Numeral 22 designates a second inverter, and the output of the first NOR gate 15 is inputted to the input thereof.
Numeral 23 designates a third NOR gate of two inputs, and one input thereof is connected to the output of the second NOR gate 18, and the other input to the carry input terminal 10.
Numeral 24 designates a fourth NOR gate of two inputs, and the first input thereof is connected to the output of the second inverter 22, and the second input to the output of the third NOR gate 23, and the output is connected to the carry output terminal 11. In other words, the output of the fourth NOR gate 24 becomes the carry signal #CY.sub.i given to the following bit.
In the conventional one bit ALU shown in FIG. 1, an arithmetic/logic operation, to be executed responsive to the combination of the control signals S.sub.0, S.sub.1, S.sub.2, S.sub.3 and S.sub.4 inputted to the control signal lines 5 to 9, is decided.
FIG. 2 is a table showing a relation between the arithmetic/logic operation executed by the conventional one bit ALU and signals inputted to the respective control signal lines 5 to 9.
For example, when logic operation "OR" is executed, , "0, 1, 1, 1, 0" as the control signals S.sub.4, S.sub.3, S.sub.2, S.sub.1, S.sub.0 are inputted respectively to the control signals 9 to 5, as shown in FIG. 2. When logic operation "EXOR", logic operation "AND", and arithmetic operation ADD are executed respectively, "0, 0, 1, 1, 0", "0, 1, 0, 1, 1", "1, 1, 0, 0, 1" as the control signals S.sub.4 , S.sub.3 , S.sub.2 , S.sub.1 , S.sub.0 respectively inputted to the control signal lines 9 to 5 are inputted respectively.
Next, concrete explanation will be made on the operation of the conventional ALU having such a configuration as aforementioned.
At first, explanation will be made on the case where logic operation "OR" is executed.
In this case, the fact, that "0, 1, 1, 1, 0" as the control signals S.sub.4, S.sub.3, S.sub.2, S.sub.1, S.sub.0 inputted respectively to the control signal lines 9 to 5 are inputted, is as shown in FIG. 2. Here, explanation will be made on the case where the first operand signal A.sub.i inputted to the first operand input terminal 1 is "1" and the case where the signal is "0".
When "1" is inputted as the first operand signal A.sub.i to the first operand input terminal 1, the second NOR gate 18 outputs "0". Since "1" is inputted as the control signal S.sub.2, S.sub.3 to both of the control signal lines 7, 8, and "1" is inputted to the first operand input terminal, all of the inputs of either the first AND gate 13 or the second AND gate become "1" irrespective of the value of the second operand signal B.sub.i inputted to the second operand input terminal 2, and the output thereof becomes "1". Thereby, the output of the first NOR gate 15 becomes "0".
Accordingly, the first EXOR gate 19 inputs the output "0" of the first NOR gate 15 and the output "0" of the second NOR gate 18 to output "0". On the other hand, since "0" is inputted as the control signal S.sub.4 to the control signal line 9, the first NAND gate 20 outputs "1". Since the second EXOR gate 21 inputs the output "0" of the first EXOR gate 19 and the output "1" of the first NAND gate 20 to output "1", "1" is outputted as an operation result signal F.sub.i from the operation result output terminal 3.
When "0" is inputted as the first operand signal A.sub.i to the first operand input terminal 4, both the first AND gate 13 and the second AND gate 14 output "0". Thereby, the first NOR gate 15 outputs "1". Since "0" is inputted as the control signal S.sub.0 to the control signal line 5, the fourth AND gate 17 always outputs "0". Since one input of the third AND gate 16 is connected to the first inverter 12, the third AND gate 16 outputs "0" when the second operand signal B.sub.i inputted to the second operand input terminal 2 is "1" (explanation will be made later on the case where the second operand signal B.sub.i is "0").
Accordingly, since all of the three inputs of the second NOR gate 18 become "0" the output thereof becomes "1" The fact, that the first EXOR gate 19 inputs the output "1" of the first NOR gate 15 and the output "1" of the second NOR gate 18 to output "0" and thereafter "1" is outputted as the operation result output signal F.sub.i from the operation result output terminal 3, is same as in the case where the aforesaid first operand signal A.sub.i is "1".
When the second operand signal B.sub.i inputted to the second operand input terminal 2 is "0", the first inverter 12 outputs "1", and after inputting it, the third AND gate 16 outputs "1". The second NOR gate 18 inputs the output "1" of the third AND gate 16 to output "0". Thereby, since one input of the first EXOR gate 19 becomes "1" and the other input becomes "0" the first EXOR gate 19 outputs "1". At this time, since the output of the first NAND gate 20 becomes "1" the second EXOR gate 21 outputs "0" thereby, "0" is outputted as the operation result signal F.sub.i from the operation result output terminal 3.
When logic operation "EXOR" is executed, "0, 0, 1, 1, 0" are inputted as the control signals S.sub.4, S.sub.3, S.sub.2, 1, S.sub.0 respectively to the control signal lines 9 to 5.
At first, explanation will be given on the case where "0" is inputted as the first operand signal A.sub.i to the first operand input terminal 1 and "0" is inputted as the second operand signal B.sub.i to the second operand input terminal 2.
Since the control signal S.sub.3 being inputted to the control signal line 8 is "0" the first AND gate 13 outputs "0". Since the first operand signal A.sub.i being inputted to the first operand input terminal 1 is "0", the second AND gate 14 outputs "0". Thereby, both the two inputs of the first NOR gate 15 become "0" the NOR gate 15 outputs "1" Since the second operand signal B.sub.i inputted to the second operand input terminal 2 is "0", the inverter 12 outputs "1".
Accordingly, the third AND gate 16 inputs the output "1" of the inverter 12 and the signal "1" of the control signal line 6 to output "1". The second NOR gate 18 inputs this output to output "0". The first EXOR gate 19 inputs the output "1" of the NOR gate 15 and the output "0" of the NOR gate 18 to output "1". Since the output of the first EXOR gate 19 is inverted by the second EXOR gate 21, "0" is outputted as the operation result signal F.sub.i from the operation result output terminal 3.
Next, explanation will be given on the case where "1" is inputted as the first operand signal A.sub.i to the first operand input terminal 1 and "0" is inputted as the second operand signal B.sub.i to the second operand input terminal 2.
Since the control signal S.sub.3 being inputted to the control signal line 8 is "0", the first AND gate 13 outputs "0". Since the input of the inverter 12 is connected to the second operand input terminal 2, the inverter 12 outputs "1". Thereby, all of the three inputs of the second AND gate 14, that is, the outputs of the first operand input terminal 1, the control signal line 7 and the inverter 12 become "1", and the second AND gate 14 outputs "1". By inputting the output, the first NOR gate 15 outputs "0".
The second NOR gate 18 inputs signal "1" from the first operand input terminal 1 to output "0". The first EXOR gate 19 inputs the output "0" of the first NOR gate 15 and the output "0" of the second NOR gate 18 to output "0". Since the output of the first EXOR gate 19 is inverted by the second EXOR gate 21, "1" is outputted as the operation result signal F.sub.i from the operation result output terminal 3.
Next explanation will be given on the case where "0" is inputted as the first operand signal A.sub.i to the first operand input terminal 1 and "1" is inputted as the second operand signal B.sub.i to the second operand input terminal 2.
Since the control signal S.sub.3 being inputted to the control signal line 8 is "0", the first AND gate 13 outputs "0". The second AND gate 14 inputs signal "0" from the first operand input terminal 1 to output "0". Accordingly, since both of the two inputs of the first NOR gate 15 become "0", the NOR gate 15 outputs "1". Since the input of the inverter 12 is connected to the second operand input terminal 2, the inverter 12 outputs "0". The third AND gate 16 inputs the output of the inverter 12 to output "0". Since the control signal S.sub.0 being inputted to the control signal line 5 is "0", the fourth AND gate 17 outputs "0".
Accordingly, all of the three inputs of the second NOR gate 18, that is, the output of the third AND gate 16, the output of the fourth AND gate 17 and the first operand input terminal 1 become "0", and the second NOR gate 18 outputs "1". The first EXOR gate 19 inputs the output "1" of the first NOR gate 15 and the output "1" of the second NOR gate 18 to output "0". Since the output of the first EXOR gate 19 is inverted by the second EXOR gate 21, "1" is outputted as the operation result signal F.sub.i from the operation result output terminal 3.
At last, explanation will be given on the case where "1" is inputted as the first operand signal A.sub.i to the first operand input terminal 1 and "1" is inputted as the second operand signal B.sub.i to the second operand input terminal 2.
Since the control signal S.sub.3 being inputted to the control signal line 8 is "0", the first AND gate 13 outputs "0". Since the input of the inverter 12 is connected to the second operand input terminal 2, the inverter 12 outputs "0". By inputting the output of the inverter 12, the second AND gate 14 outputs "0". Thereby, both of the two inputs of the first NOR gate 15 become "0", and the first NOR gate outputs "1". The third AND gate 16 inputs the output "0" of the inverter 12 and outputs "0". The second NOR gate 18 inputs the output of the third AND gate 16 and outputs "0". The first EXOR gate 19 inputs the output "1" of the first NOR gate 15 and the output "0" of the second NOR gate 18 and outputs "1". Since the output of the first EXOR gate 19 is inverted by the second EXOR gate 21, "0" is outputted as the operation result signal F.sub.i from the operation result output terminal 3.
When logic operation "AND" is executed, "0, 1, 0, 1, 1" are inputted as the control signals S.sub.4, S.sub.3, S.sub.2, S.sub.1, S.sub.0 respectively to the control signal lines 9 to 5.
At this time, since the control signal S.sub.2 having been inputted to the control signal line 7 is "0", the second AND gate 14 always outputs "0". To the one input of the fourth AND gate 17 and to the one input of the third AND gate 16, the second operand signal B.sub.i inputted to the second operand input terminal 2 and a signal obtained by inverting the second operand signal B.sub.i are inputted respectively. To the other input of the fourth AND gate 17 and to the other input of the third AND gate 16, since the control signals S.sub.0, S.sub.1 inputted to the control signal lines 5, 6 which are both "1" are being inputted, either the output of the fourth AND gate 17 or the output of the third AND gate 16 becomes "1".
Accordingly, the second NOR gate 18 always outputs "0". On that assumption, explanation will be made on the respective combinations of signals inputted to the first operand input terminal 1 and to the second operand input terminal 2.
At first, explanation will be made on the case where "0" is inputted as the first operand signal A.sub.i to the first operand input terminal 1, and "0" is inputted as the second operand signal B.sub.i to the second operand input terminal 2.
The first AND gate 13 inputs "0" as the first operand signal A.sub.i from the first operand input terminal 1 to output "0". The first NOR gate 15 inputs the output "0" of the first AND gate 13 and the output "0" of the second AND gate 14 to output "1". The first EXOR gate 19 inputs the output "1" of the first NOR gate 15 and the output "0" of the second NOR gate 18 to output "1". Since the output of the first EXOR gate 19 is inverted by the second EXOR gate 21, "0" is outputted as the operation result signal F.sub.i from the operation result output terminal 3.
Next, explanation will be given on the case where "1" is inputted to the first operand input terminal 1 and "0" is inputted to the second operand input terminal 2.
The first AND gate 13 inputs a signal "0" having been inputted to the second operand input terminal 2 to output "0". The first NOR gate 15 inputs the output "0" of the AND gate 13 and the output "0" of the second AND gate 14 to output "1". The first EXOR gate 19 inputs the output "1" of the first NOR gate 15 and the output "0" of the second NOR gate 18 to output "1". Since the output of the first EXOR gate 19 is inverted by the second EXOR gate 21, "0" is outputted from the operation result output terminal 3.
Next, explanation will be given on the case where "0" is inputted as the first operand signal A.sub.i to the first operand input terminal 1 and "1" is inputted as the second operand signal B.sub.i to the second operand input terminal 2.
The first AND gate 13 inputs "0" as the first operand signal A.sub.i from the first operand input terminal 1 to output "0". The first NOR gate 15 inputs the output "0" of the first AND gate 13 and the output "0" of the second AND gate 14 to output "1". The first EXOR gate 19 inputs the output "1" of the first NOR gate 15 and the output "0" of the second NOR gate 18 to output "1". Since the output of the first EXOR gate 19 is inverted by the second EXOR gate 21, "0" is outputted as the operation result signal F.sub.i from the operation result output terminal 3.
At last, explanation will be given on the case where "1" is inputted as the first operand signal A.sub.i to the first operand input terminal 1 and "1" is inputted as the second operand signal B.sub.i to the second operand input terminal 2.
Since both of the first operand signal A.sub.i inputted to the first operand input terminal 1 and the second operand signal B.sub.i inputted to the second operand input terminal 2 are "1", and the control signal S.sub.2 inputted to the control signal line 8 is "1", the first AND gate 13 outputs "1". After inputting the output of the first AND gate 13, the first NOR gate 15 outputs "0". The first EXOR gate 19 inputs the output "0" of the first NOR gate 15 and the output "0" of the second NOR gate 18 to output "0". Since the output of the first EXOR gate 19 is inverted by the second EXOR gate 21, "1" is outputted as the operation result signal F.sub.i from the operation result output terminal 3.
When arithmetic operation "ADD" is executed, "1, 1, 0, 1" are inputted as the control signal S.sub.4, S.sub.3, S.sub.2, S.sub.1, S.sub.0 inputted to the control signal lines 9 to 5.
At this time, the second AND gate 14 inputs "0" as the control signal S.sub.2 from the control signal line 7 to always output "0", and the third AND gate 16 inputs "0" as the control signal S.sub.1 from the control signal line 6 to always output "0". Since the control signal S.sub.4 inputted to the control signal line 9 is "1", the first NAND gate 20 inverts the carry signal #CY.sub.i-1 from the preceding bit inputted from the carry input terminal 10 to output it to the second EXOR gate 21.
Accordingly, when the carry signal #CY.sub.i-1 from the preceding bit is "0", the second EXOR gate 21 inverts the output of the first EXOR gate 19 to output it as the operation result signal F.sub.i from the operation result output terminal 3, and when the carry signal #CY.sub.i-1 from the preceding bit is "1", the second EXOR gate 21 outputs the output of the first EXOR gate 19 intact as the operation result signal F.sub.i from the operation result output terminal 3. On that assumption, the explanation will be given on the combination of the first operand signal A.sub.i and the second operand signal B.sub.i respectively inputted to the first operand input terminal 1 and the second operand input terminal 2.
At first, explanation will be given on the case where "0" is inputted as the first operand signal A.sub.i to the first operand input terminal 1 and "0" is inputted as the second operand signal B.sub.i to the second operand input terminal 2.
The first AND gate 13 inputs "0" from the first operand input terminal 1 as the first operand signal A.sub.i to output "0". Thereby, the first NOR gate 15 inputs the output "0" of the first AND gate 13 and the output "0" of the second AND gate 14 to output "1". The fourth AND gate 17 inputs a signal "0" of the second operand input terminal 2 to output "0". Thereby, since all of the three inputs of the second NOR gate 18, that is, the output of the third AND gate 16, the output of the fourth AND gate 17 and the signal of the first operand input terminal 1 become "0", the second NOR gate 18 outputs "1". The first EXOR gate 19 inputs the output "1" of the first NOR gate 15 and the output "1" of the second NOR gate 18 to output "0".
At this time, when the carry signal #CY.sub.i-1 from the preceding bit inputted from the carry input terminal 10 is "0", the second EXOR gate 21 inverts the output "0" of the first EXOR gate 19 and outputs "1" from the operation result output terminal 3 as the operation result signal F.sub.i. On the contrary, when the carry signal #CY.sub.i-1 from the preceding bit inputted to the carry input terminal 10 is "1", the second EXOR gate 21 outputs intact the output "0" of the first EXOR gate 19 from the operation result output terminal 3 as the operation result signal F.sub.i.
When the carry signal #CY.sub.i-1 is "1", the second inverter 22 inputs the output, "1" of the first NOR gate 15 and outputs "0" obtained by inverting the output "1" of the first NOR gate 15 to the fourth NOR gate 24. The third NOR gate 23 inputs the output "1" of the second NOR gate 18 to output "0" to the fourth NOR gate 24. Accordingly, since both of the two inputs of the fourth NOR gate 24 become "0", "1" is outputted from the carry signal output terminal 11 as the carry signal #CY.sub.i given to the following bit.
Next, explanation will be given on the case where "1" is inputted as the first operand signal A.sub.i to the first operand input terminal 1 and "0" is inputted as the second operand signal B.sub.i to the second operand input terminal 2.
The first AND gate 13 inputs "0" from the second operand input terminal 2 as the second operand signal B.sub.i to output "0". The first NOR, gate 15 inputs the output "0" of the first AND gate 13 and the output "0" of the second AND gate 14 to output "1". The second NOR gate 18 inputs "1" from the first operand input terminal 1 as the first operand signal A.sub.i to output "0". Accordingly, the first EXOR gate 19 inputs the output "1" of the first NOR gate 15 and the output "0" of the second NOR gate 18 to output "1".
At this time, when the carry signal #CY.sub.i-1 from the preceding bit inputted from the carry input terminal 10 is "0", the second EXOR gate 21 inverts the output "1" of the first EXOR gate 19 to output "0" from the operation result output terminal 3 as the operation result signal F.sub.i. On the contrary, when the carry signal #CY.sub.i-1 from the preceding bit inputted from the carry input terminal 10 is "1", the second EXOR gate 21 outputs intact the output "1" of the first EXOR gate 19 from the operation result output terminal 3 as the operation result signal F.sub.i.
The second inverter 22 inputs and inverts the output "1" of the first NOR gate 15 to output "0" to the fourth NOR gate 24. On the other hand, the output of the second NOR gate 18 is "0", the third NOR gate 23 inverts the carry signal #CY.sub.i-1 from the preceding bit inputted from the carry input terminal 10 to output it to the fourth NOR gate 24. Accordingly, the carry signal #CY.sub.i-1 from the preceding bit inputted from the carry input terminal 10 is "1", since both of the two inputs of the fourth NOR gate 24 become "0", the fourth NOR gate 24 outputs "1" from the carry output terminal 11 as the carry signal #CY.sub.i given to the following bit. On the contrary, when the carry signal #CY.sub.i-1 from the preceding bit inputted from the carry input terminal 10 is "0", the third NOR gate 23 outputs "1" to the fourth NOR gate 24. The fourth NOR gate 24 inputs the output of the third NOR gate 23 and outputs "0" from the carry output terminal 11 as the carry signal #CY.sub.i given to the following bit.
Next, explanation will be given on the case where "0" is inputted as the first operand signal A.sub.i to the first operand input terminal 1, and "1" is inputted as the second operand signal B.sub.i to the second operand input terminal 2.
The first AND gate 13 inputs "0" from the first operand input terminal 1 as the first operand signal A.sub.i to output "0". The first NOR gate 15 inputs the output "0" of the first AND gate 13 and the output "0" of the second AND gate 14 to output "1". The fourth AND gate 17 inputs "1" as the second operand signal B.sub.i from the second operand input terminal 2 and "1" as the control signal S.sub.0 from the control signal line 5 to output "1". The second NOR gate 18 inputs the output of the fourth AND gate 17 to output "0".
Therefore, the first EXOR gate 19 inputs the output "1" of the first NOR gate 15 and the output "0" of the second NOR gate 18 to output "1".
Explanation on the operation after this will be omitted because it is same as that of the case where "1" is inputted as the first operand signal A.sub.i the first operand input terminal 1 and "0" is inputted as the second operand signal B.sub.i to the second input terminal 2.
At last, explanation will be made on the case where "1" is inputted as the first operand signal A.sub.i to the first operand input terminal 1 and "1" is inputted as the second operand signal B.sub.i to the second operand input terminal 2.
The first AND gate 13 inputs "1" as the first operand signal A.sub.i from the first operand input terminal 1, "1" as the second operand signal B.sub.i from the second operand input terminal 2 and "1" as the control signal S.sub.2 from the control signal line 8 respectively to output "1". The first NOR gate 15 inputs the output of the first AND gate 13 to output "0". The second NOR gate 18 inputs "1" from the first operand input terminal 1 as the first operand signal A.sub.i to output "0".
Accordingly, the first EXOR gate 19 inputs the output "0" of the first NOR gate 15 and the output "0" of the second NOR gate 18 to output "0".
At this time, when the carry signal #CY.sub.i-1 from the preceding bit inputted from the carry input terminal 10 is "0", the second EXOR gate 21 inverts the output "0" of the EXOR gate 19 and outputs "1" from the operation result output terminal 3 as the operation result signal F.sub.i. On the contrary, when the carry signal #CY.sub.i-1 from the preceding bit inputted from the carry input terminal 10 is "1", the second EXOR gate 21 outputs intact the output "0" of the first EXOR gate 19 from the operation result output terminal 3 as the operation result signal F.sub.i.
The second inverter 22 inputs and inverts the output "0" of the first NOR gate 15 and outputs "1" to the fourth NOR gate 24. The fourth NOR gate 24 inputs the output of the second inverter 22 and outputs "0" from the carry output terminal 11 as the carry signal #CY.sub.i given to the following bit.
By the way, the conventional one bit ALU shown in FIG. 1 is composed of about 50 transistors. But, when microcomputer is configured as an LSI obtained by integrating circuits on one chip, it is expected that the number of transistors used as ALU is made as small as possible so that ALU does not occupy the substrate area excessively. It has become an important point when such circumstances is taken into consideration that a microcomputer is made to have a sophisticated function sequentially from 8 bits to 16 bits, and to 32 bits recently.
And the conventional ALU cannot drive a data bus because the driving ability of the EXOR gate of itself is low, and a bus driver is required for outputting an operation result data to a data bus.